1. Field of the Invention
The present invention relates to a heterojunction field effect transistor (to be abbreviated as HJFET hereinafter) and, more particularly, an HJFET having good controllability for a threshold voltage.
2. Description of the Prior Art
FIG. 1A is a view showing the element structure of an HJFET according to the prior art. This HJFET is reported in, e.g., U. K. Mishra et al, IEEE Transactions on Microwave Theory and Techniques, Vol. 46, page 756, 1998.
Referring to FIG. 1A, a buffer layer 91 comprised of a multilayered structure of aluminum nitride (AlN) and gallium nitride (GaN) is formed in contact with a sapphire (Al2O3) substrate 90, and a channel layer 92 made of gallium nitride (GaN) is formed in contact with the buffer layer 91. A gate insulating layer 93 made of undoped AlGaN is formed in contact with the GaN channel layer 92. Two-dimensional electrons 94 are generated in the channel layer 92 to establish ohmic contact between a source electrode 97S formed on the gate insulating layer 93 and a drain electrode 97D, and the channel layer 92. A gate electrode 99 is formed between the source electrode 97S and drain electrode 97D to establish Schottky contact with the gate insulating layer 93.
FIG. 1B is a schematic diagram of conduction band energy between the gate electrode 99 and GaN channel layer 92 of the prior art HJFET. The lattice constant (a-axis) of AlGaN forming the gate insulating layer 93 is shorter than that of GaN forming the buffer layer 91. Hence, a piezoelectric field is formed to extend from the substrate toward the surface. Even when the gate voltage is 0 V, the two-dimensional electrons 94 are generated in the channel layer 92. Therefore, in the prior art HJFET, the threshold voltage is difficult to control, and the prior art HJFET usually forms a depletion type FET. An enhancement type FET is thus difficult to fabricate.
The present invention has been made to solve the above problems of the prior art, and has as its object to provide an HJFET structure that can form a depletion type FET and an enhancement type FET separately by improving the controllability for the threshold voltage.
In order to achieve the above object, according to the main aspect of the present invention, there is provided a heterojunction field effect transistor having a buffer layer including at least one GaN layer, a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode on a substrate, wherein the channel layer has a composition of InzGa1xe2x88x92zN (0xe2x89xa6z less than 1) and the gate insulating layer is an InAlGaN layer, and the source and drain electrodes are in ohmic contact with the channel layer and the gate electrode and the gate insulating layer are in Schottky contact with each other.
In the prior art, the threshold voltage is difficult to control due to the following reason. Namely, the lattice constant (a-axis) of AlGaN forming the gate insulating layer is shorter than that of GaN forming the buffer layer. Hence, two-dimensional electrons are generated in the channel layer due to a piezoelectric effect. To enable fabrication of a depletion type FET and an enhancement type FET separately by improving the controllability for the threshold voltage, the gate insulating layer may be made of a material the d-axis length of which can be changed around the lattice constant (a-axis) of GaN. This can be realized by setting, in InxAlyGa1xe2x88x92xxe2x88x92yN as a four-element type semiconductor, the composition ratio of x to y appropriately.
In the present invention, in an HJFET having a GaN buffer layer and an InzGa1xe2x88x92zN channel layer (0xe2x89xa6z less than 1), InxAlyGa1xe2x88x92xxe2x88x92yN (x greater than 0, y greater than 0, x+yxe2x89xa61) is used to form a gate insulating layer.
Even if InzGa1xe2x88x92zN (zxe2x89xa00) is used to form the channel layer, a good crystal free from crystal dislocation is formed at a small film thickness because of the effect of the strain layer. In this case, it is already known that the a-axis length of the InzGa1xe2x88x92zN (zxe2x89xa00) layer is equal to that of the GaN buffer layer. The thickness of the channel layer satisfying this condition is 300 xc3x85 or less and preferably 30 xc3x85 to 200 xc3x85 for z=0.1, and is 100 xc3x85 or less and preferably 30 xc3x85 to 80 xc3x85 for z=0.2.
The a-axis length of InxAlyGa1xe2x88x92xxe2x88x92yN is expressed as:
a(x, y)=3.548x+3.112y+3.189(1xe2x88x92xxe2x88x92y)xc3x85xe2x80x83xe2x80x83(1)
The condition under which the a-axis length of InxAlyGa1xe2x88x92xxe2x88x92yN becomes smaller than that of the GaN buffer layer (a=3.189 xc3x85) is: a(x, y) less than 3.189 xc3x85. Hence,
y greater than 4.66xxe2x80x83xe2x80x83(2)
At this time, a piezoelectric field is formed to extend from the substrate toward the surface, in the same manner as in the prior art, and accordingly a depletion type FET becomes easy to fabricate.
The condition under which the a-axis length of InxAlyGa1xe2x88x92xxe2x88x92yN becomes larger than that of the GaN buffer layer is: a(x, y) greater than 3.189 xc3x85. Hence,
y less than 4.66xxe2x80x83xe2x80x83(3)
At this time, a piezoelectric field is formed to extend from the surface toward the substrate, unlike in the prior art. Hence, when the gate voltage is 0 V, the channel layer is depleted, and an enhancement type FET becomes easy to fabricate.
Preferably, the difference in the a-axis length between InxAlyGa1xe2x88x92xxe2x88x92yN forming the gate insulating layer and GaN forming the buffer layer can be set to be equal to the difference in a-axis length between AlN (a=3.112 xc3x85) and GaN (a=3.189 xc3x85) or less. Then, a critical thickness with which crystal dislocation occurs increases, so that controllability for the threshold voltage is improved. The condition under which the difference in the a-axis length between InxAlyGa1xe2x88x92xxe2x88x92yN and GaN becomes smaller than the difference in a-axis length between AlN and GaN is |a(x, y)xe2x88x923.189| less than 3.189xe2x88x923.112 xc3x85. Hence,
|yxe2x88x924.66x| less than 1xe2x80x83xe2x80x83(4)
More preferably, the a-axis length of InxAlyGa1xe2x88x92xxe2x88x92yN becomes equal to that of the GaN buffer layer. The condition for this is: a(x, y)=3.189 xc3x85. Accordingly, y=4.66x can be obtained. Since crystal dislocation does not occur in this case, the thickness of the gate insulating layer can become arbitrary, so that controllability for the threshold voltage is improved greatly. More practically, assuming that an error within the range of xe2x88x925% to +5% is allowed as a deviation of the ratio of mixed crystal from the lattice matching condition, this condition is expressed as:
|yxe2x88x924.66x| less than 0.05xe2x80x83xe2x80x83(5)
To make this gate insulating layer serve as a good gate insulating layer having a small leakage current, its band gap must be larger than that of InzGa1xe2x88x92zN forming the channel layer. The band gap of InxAlyGa1xe2x88x92xxe2x88x92yN is expressed as:
Eg(x, y)=1.89x+6.2y+3.39(1xe2x88x92xxe2x88x92y)[eV]xe2x80x83xe2x80x83(6)
Meanwhile, the band gap of InzGa1xe2x88x92zN is expressed as:
Eg(z)=1.89z+3.39(1xe2x88x92z)[eV]xe2x80x83xe2x80x83(7)
Accordingly, the condition under which the band gap of InxAlyGa1xe2x88x92xxe2x88x92yN becomes larger than that of InzGa1xe2x88x92zN is Eg(x, y) greater than Eg(z). This yields the following inequality:
y greater than 0.533(xxe2x88x92z)xe2x80x83xe2x80x83(8)
The object of the present invention can also be realized by using, as the gate insulating layer, a three-element type semiconductor superlattice such as InTGa1xe2x88x92TN/AlSGa1xe2x88x92SN, In1xe2x88x92TGaTN/In1xe2x88x92SAlSN, InTAl1xe2x88x92TN/Al1xe2x88x92SGaSN, or the like. In that case, the three-element type superlattice is equivalent to a four-element type semiconductor having an average composition weighted by the total thickness of each layer.
For example, an InTGa1xe2x88x92TN/AlSGa1xe2x88x92SN superlattice, the total layer thickness of the InTGa1xe2x88x92TN portion of which is exc3x85 and the total layer thickness of the AlSGa1xe2x88x92SN portion of which is fxc3x85, has an a-axis length and band gap that are substantially equivalent to those of IneT/(exe2x88x92f)AlfS/(e+f)Ga(e(1xe2x88x92T)+f(1xe2x88x92S))/(e+f)N.
Similarly, an In1xe2x88x92TGaTN/In1xe2x88x92SAlSN superlattice, the total layer thickness of the In1xe2x88x92TGaTN portion of which is exc3x85 and the total layer thickness of the In1xe2x88x92S AlSN portion of which is fxc3x85, has an a-axis length and band gap that are substantially equivalent to those of In(e(1xe2x88x92T)+f(1xe2x88x92S))/(e+f)AlfS/(e+f)GaeT/(e+f)N, and an InTAl1xe2x88x92TN/Al1xe2x88x92SGaSN superlattice, the total layer thickness of the InTAl1xe2x88x92TN portion of which is exc3x85 and the total layer thickness of the Al1xe2x88x92SGaSN portion of which is fxc3x85, has an a-axis length and band gap that are substantially equivalent to those of IneT/(e+f)Al(e(1xe2x88x92T)+f(1xe2x88x92S))/(e+f)GafS/(e+f)N.
Therefore, the above discussion made concerning InxAlyGa1xe2x88x92xxe2x88x92yN applies to a three-element type semiconductor superlattice as well.
To form the substrate used in the present invention, for example, silicon (Si), gallium arsenide (GaAs) or the like is used, and Al2O3 or silicon carbide (SiC) is particularly preferable.
As is apparent from the above description, according to the present invention, the a-axis length of the gate insulating film InxAlyGa1xe2x88x92xxe2x88x92yN (x greater than 0, y greater than 0, x+yxe2x89xa61) can be made larger or smaller than that of GaN by changing the mixed crystal ratio of x to y. As a result, an enhancement type FET and a depletion type FET can be made separately. Moreover, the gate insulating film can be lattice-matched with GaN, so that the degree of freedom of the thickness of the gate insulating layer is improved and controllability for the threshold voltage is greatly improved, thereby largely contributing to an improvement in performance of the HJFET.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative examples.